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X84041 1 micro port saver e 2 prom 4k X84041 mps ? e 2 prom description the X84041 micro port saver is a 4096-bit cmos e 2 prom designed for a direct interface to port limited microcontroller or i/o limited microprocessor designs. the X84041 provides all of the benefits of serial memo- ries, such as low cost, low power, low voltage operation, and small package size, while featuring higher data transfer rates and reduced interface code requirements without the need for a dedicated serial bus. the X84041 is organized as a 512 x 8, but is also suitable in 16-bit or 32-bit environments, due to the bit serial nature of the interface. the X84041 directly connects to the processor bus and communicates over a single data line using a sequence of standard bus read and write operations. this elimi- nates the need for dedicated port pins, parallel to serial converters, complicated asic implementations, or other glue logic, lowering system cost. features ? direct interface to micros eliminates i/o port requirements no interface glue logic required eliminates need for parallel to serial converters ? 3.3mbps data transfer rate ? low power cmos 2.7v to 5.5v operation standby current less than 50 m a active current less than 1ma ? 45ns read access time ? 8-byte page write mode ? typical nonvolatile write cycle time: 5ms ? high reliability 100,000 endurance cycles guaranteed data retention: 100 years ? 8-lead pdip, 8-lead soic, and 14-lead tssop packages ? xicor, inc. 1994, 1995, 1996 patents pending characteristics subject to change without notice 2704-4.4 6/12/96 t3/c1/d0 ns ce i/o h.v. generation timing & control eeprom array 512 x 8 command decode and control logic x dec y decode data register wp 2704 ill f02 oe we pin names i/o data input/output ce chip enable input oe output enable input we write enable input wp write protect input v cc supply voltage v ss ground nc no connect 2704 pgm t01 pin configuration block diagram a pplication n otes and d evelopment s ystem available an10 ? an17 ? an57 ? xk84 v cc nc oe we 2704 ill f01.2 ce i/o wp v ss 1 2 3 4 8 7 6 5 X84041 dip/soic 1 2 3 4 5 6 7 14 13 12 11 10 9 8 2704 ill f02a.1 tssop X84041 ce i/o nc nc nc wp v ss v cc nc nc nc nc oe we
X84041 2 a write protect ( wp ) pin provides hardware protection against inadvertent writes to the memory. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data re- tention is greater than 100 years. pin descriptions chip enable ( ce ce ce ce ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, the chip is dese- lected, the i/o pin is in the high impedance state, and unless a nonvolatile write operation is underway, the X84041 is in the standby power mode. output enable ( oe oe oe oe oe ) the output enable input must be low to enable the output buffer and to read data from the X84041 on the i/o line. write enable ( we we we we we ) the write enable input must be low to write either data or command sequences to the X84041. data in/data out (i/o) data and command sequences are serially written to or serially read from the X84041 through the i/o pin. write protect ( wp wp wp wp wp ) when the write protect input is low, nonvolatile writes to the X84041 are disabled. when wp is high, all functions, including nonvolatile writes, operate normally. if a nonvolatile write cycle is in progress, wp going low will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles. device operation the X84041 is a serial 512 x 8 bit e 2 prom designed to interface directly with most microprocessor buses. stan- dard ce , oe , and we signals control the read and write operations, and a single l/o line is used to send and receive data and commands serially. data timing data input on the l/o line is latched on the rising edge of either we or ce , whichever occurs first. data output on the l/o line is active whenever both oe and ce are low. care should be taken to ensure that we and oe are never both low while ce is low. read sequence a read sequence consists of sending a 16-bit address followed by the reading of data serially. the address is written by issuing 16 separate write cycles ( we and ce low, oe high) to the part without a read cycle be- tween the write cycles. the address is sent serially, most significant bit first, over the i/o line. note that this sequence is fully static, with no special timing restric- tions, and the processor is free to perform other tasks on the bus whenever the X84041 ce pin is high. once the 16 address bits are sent, a byte of data can be read on the i/o line by issuing 8 separate read cycles ( oe and ce low, we high). at this point, issuing a reset sequence will terminate the read sequence, otherwise the X84041 will await further reads in the sequential read mode. sequential read the byte address is automatically incremented to the next higher address after each byte of data is read. the data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. when the highest address is reached ($1ff), the ad- dress counter rolls over to address $000 and reading may be continued indefinitely. reset sequence the reset sequence resets the X84041 and sets an internal write enable latch. a reset sequence can be sent at any time by performing a read/write 0/read se- quence (see figs. 1 and 2). this sequence breaks the multiple read or write cycle sequences that are normally used when reading from or writing to the part. this sequence can be used at any time to interrupt or end a sequential read or page load. as soon as the write 0 cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). the second read cycle in this sequence, and any further read cycles, will read a high on the l/o pin until a valid read sequence is issued. the reset sequence must be issued at the beginning of both read and write sequences to be sure the X84041 initiates these operations properly.
X84041 3 figure 1. read sequence ce oe we i/o (in) "0" reset load address read data x xxxxx x a8 a7 a6 a5 a4 a3 a2 a1 a0 i/o (out) 2704 ill f03 d7 d6 d5 d4 d3 d2 d1 d0 write sequence a nonvolatile write sequence consists of sending a reset sequence, a 16-bit address (the first 7 of which are dont cares), up to 8 bytes of data, and then a special start nonvolatile write cycle command sequence. the reset sequence is issued first (as described in the reset sequence section) to set the internal write enable latch. the address is written serially by issuing 16 separate write cycles ( we and ce low, oe high) to the part without any read cycles between the writes. the ad- dress is sent serially, most significant bit first, on the l/o pin. up to eight bytes of data are written by issuing either 8, 16, 24, 32, 40, 48, 56, or 64 separate write cycles. again, no read cycles are allowed between writes. the nonvolatile write cycle is initiated by issuing a special read/write 1/read sequence. the first read cycle ends the page load, then the write 1 followed by a read starts the nonvolatile write cycle. the X84041 recognizes 8- byte pages beginning at addresses xxxxxx000. when sending data to the part, attempts to exceed the upper address of the page will result in the address counter wrapping-around to the first address on the page, where data loading can continue. for this reason, send- ing more than 64 consecutive data bits will result in overwriting previous data. a nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. the internal write enable latch is reset when the nonvolatile write cycle is completed to prevent inadvert- ent writes. note that this sequence is fully static, with no special timing restrictions. the processor is free to perform other tasks on the bus whenever the chip enable pin ( ce ) is high. nonvolatile write status the status of a nonvolatile write cycle can be deter- mined at any time by simply reading the state of the l/o pin on the X84041. this pin is read when oe and ce are low and we is high. during a nonvolatile write cycle the l/o pin is low. when the nonvolatile write cycle is complete, the l/o pin goes high. a reset sequence can also be issued during a nonvolatile write cycle with the same result: i/o is low as long as a nonvolatile write cycle is in progress, and l/o is high when the nonvola- tile write cycle is done.
X84041 4 figure 2. write sequence ce oe we i/o (in) "0" "0" "1" reset load address load data start nonvolatile write x xxxxx x a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i/o (out) 2704 ill f04 symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance write protection the following circuitry has been included to prevent inadvertent nonvolatile writes: the internal write enable latch is reset upon power-up. a reset sequence must be issued to set the internal write enable latch before starting a write sequence. a special start nonvolatile write command sequence is required to start a nonvolatile write cycle. the internal write enable latch is reset automatically at the end of a nonvolatile write cycle. the internal write enable latch is reset and remains reset as long as the wp pin is low, which blocks all nonvolatile write cycles.
X84041 5 d.c. operating characteristics (v cc = 5v 10%) (over the recommended operating conditions, unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc1 v cc supply current (read) 1 ma oe = v il , we = v ih , i/o = open, ce clocking @ 2mhz i cc2 v cc supply current (write) 3 ma i cc during nonvolatile write cycle all inputs at cmos levels i sb v cc standby current 50 m a ce = v cc , other inputs = v cc or v ss v cc = 5v 10% i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v ll (1) input low voltage C1 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma, v cc = 5v 10% v oh output high voltage v cc C 0.8 v i oh = C1ma, v cc = 5v 10% 2704 pgm t04.3 *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* temperature under bias .................. C65 c to +135 c storage temperature ....................... C65 c to +150 c terminal voltage with respect to v ss ....................................... C1v to +7v dc output current ............................................... 5ma lead temperature (soldering, 10 seconds) ...... 300 c notes: (1) v il min. and v ih max. are for reference only and are not tested. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c 2704 pgm t02.2 ? contact factory for availability. supply voltage limits X84041 5v 10% X84041 C 3 3v 10% X84041 C 2.7 ? 2.7v to 5.5v 2704 pgm t03.2
X84041 6 d.c. operating characteristics (v cc = 3v 10%) (over the recommended operating conditions, unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc1 v cc supply current (read) 250 m a oe = v il , we = v ih , i/o = open, ce clocking @ 2mhz i cc2 v cc supply current (write) 1 ma i cc during nonvolatile write cycle all inputs at cmos levels i sb1 v cc standby current 10 m a ce = v cc , other inputs = v cc or v ss v cc = 3v 10% i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v ll (1) input low voltage C1 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 1ma, v cc = 3v 10% v oh output high voltage v cc C 0.4 v i oh = C400 m a, v cc = 3v 10% 2704 pgm t05.2 notes: (2) periodically sampled, but not 100% tested. power-up timing symbol parameter max. units t pur (3) power-up to read operation 2 ms t puw (3) power-up to write operation 5 ms 2704 pgm t07 a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 5ns input and output v cc x 0.5 timing levels 2704 pgm t08.1 notes: (1) v il min. and v ih max. are for reference only and are not tested. capacitance t a = +25 c, f = 1mhz, v cc = 5v symbol parameter max. units test conditions c i/o (2) input/output capacitance 8 pf v i/o = 0v c in (2) input capacitance 6 pf v in = 0v 2704 pgm t06.2 notes: (3) time delays required from the time the v cc is stable until the specific operation can be initiated. periodically sampled, but not 100% tested.
X84041 7 equivalent a.c. load circuits notes: (4) periodically sampled, but not 100% tested. t hz and t ohz are measured from the point where ce or oe goes high (whichever occurs first) to the time when i/o is no longer being driven into a 5pf load. a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) read cycle limits C X84041 v cc = 5v 10% v cc = 3v 10% symbol parameter min. max. min. max. units t rc read cycle time 300 300 ns t ce ce access time 45 65 ns t oe oe access time 45 65 ns t low ce low time 70 70 ns t high ce high time 70 70 ns t lz (4) ce low to output in low z 0 0 ns t hz (4) ce high to output in high z 0 30 0 35 ns t olz (4) oe low to output in low z 0 0 ns t ohz (4) oe high to output in high z 0 30 0 35 ns t oh output hold from ce or oe high 0 0 ns t wes we high setup time 25 25 ns t weh we high hold time 25 25 ns 2704 pgm t09.3 5v 30pf 2.06k w 3.03k w output 2704 ill f05.2 3v 30pf 2.39k w 4.58k w output 2704 ill f05a.3
X84041 8 read cycle ce we t wes oe 2704 ill f06 t high t ce t oe t olz t oh t weh high z data t ohz t hz t lz t low t rc i/o write cycle limits C X84041 v cc = 5v 10% v cc = 3v 10% symbol parameter min. max. min. max. units t nvwc (5) nonvolatile write cycle time 10 10 ms t wc write cycle time 300 300 ns t wp we pulse width 30 30 ns t wph we high recovery time 200 200 ns t cs write setup time 0 0 ns t ch write hold time 0 0 ns t cp ce pulse width 30 30 ns t cph ce high recovery time 200 200 ns t oes oe high setup time 50 50 ns t oeh oe high hold time 50 50 ns t ds (6) data setup time 30 30 ns t dh (6) data hold time 5 5 ns t wpcs (7) wp high before ce 500 500 ns t wpch (7) wp high after ce 500 500 ns t wpws (7) wp high before we 500 500 ns t wpwh (7) wp high after we 500 500 ns 2704 pgm t10.3 notes: (5) t nvwc is the time from the falling edge of oe or ce (whichever occurs last) of the second read cycle in the start nonvolatile write cycle sequence until the self-timed, internal nonvolatile write cycle is completed. (6) data is latched into the X84041 on the rising edge of ce or we , whichever occurs first. (7) periodically sampled, but not 100% tested.
X84041 9 25 ce ce ce ce ce controlled write cycle ce oe t wph we 2704 ill f07 wp i/o t oes t cph t oeh t ch t wpch high z data t ds t dh t cp t wp t wpcs t cs t wc we we we we we controlled write cycle ce oe t wph we 2704 ill f08 wp i/o t oes t cph t ch t oeh t wpwh high z data t ds t dh t cp t wp t wpws t cs t wc
X84041 10 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X84041 11 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 3926 fhd f22.1 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
X84041 12 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f32
X84041 13 device v cc range blank = 4.5v to 5.5v 3 = 2.7v to 3.3v 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c package p = 8-lead plastic dip s = 8-lead soic v = 14-lead tssop X84041 x x -x limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information
X84041 14 u.s. sales offices corporate office xicor inc. 1511 buckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne @smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se @smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma @smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc @smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc @smtpgate.xicor.com international sales offices singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka @smtpgate.xicor.com ( ) = country code europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk @smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm @smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp @smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com xicor, inc., marketing dept. 1511 buckeye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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